DocPile 3.1.2
Docpile (SDMS clone) is a PHP-based document management system that allows multiple people to share documents and keep track of revisions.
Users can upload and download documents, grant per-file, -user, or -folder access privileges, and send notification emails when documents are being updated.
istrators can create access groups, each responsible for a different set of folders and users.
Folder Access Privileges
VHDL Modelling Course
From the digital design course you should already have a textbook which talks about many of the features of the language. Because of this, I have assigned the IEEE Standard VHDL Language Reference Manual as the textbook for this course. This is not that readable, but it is the definitive reference for the language. MSU currently has access towww.ewalkins.com
VHDL Modelling Course
From the digital design course you should already have a textbook which talks about many of the features of the language. Because of this, I have assigned the IEEE Standard VHDL Language Reference Manual as the textbook for this course. This is not that readable, but it is the definitive reference for the language. MSU currently has access towww.ewalkins.com
NetXMS is new and rapidly developing monitoring system, released under GPL2 license. NetXMS project can be used for monitoring entire IT infrastructure, starting with SNMP-capable hardware (like switches and routers) and ending with applications on your servers. NetXMS is an extremely reliable and powerful monitoring system, enabling you to improve your network availability and service levels.
The system has three-tier architecture: the information is collected by monitoring agents (either our own high-performance agents or SNMP agents) and delivered to monitoring server for processing and storing. Network istrator can access collected data using Windows-based Management Console, WEB Interface or Management Console for PocketPC.
VHDL Verification Course
Verification is an important part of any ASIC design cycle. It's important that complex designs are simulated fully before prototypes are built, as it's difficult to find bugs in silicon and going through additional layout cycles is costly and time consuming
www.ewalkins.com
VHDL Language Guide
The powerful and versatile VHDL-based FPGA design entry, simulation and synthesis solution, PeakFPGA, has now been incorporated into Altium's new vendor-independent system for designing embedded systems on FPGAwww.ewalkins.com
VHDL TestBench Generator
Just copy your ENTITY in the textbox below and decide if you want to get a Synopsys VSS-Startfile and a VSS-Tracefile.
The ENTITY must be written in correct VHDL syntax!www.ewalkins.com
libgnomeuimm 2.20.1
libgnomeuimm is a C++ wrapper for GNOME.
Installation:
The simplest way to compile this package is:
1. `cd' to the directory containing the package's source code and type `./configure' to configure the package for your system.
Running `configure' might take a while. While running, it prints some messages telling which features it is checking for.
2. Type `make' to compile the package.
3. Optionally, type `make check' to run any self-tests that come with the package.
4. Type `make install' to install the programs and any data files and documentation.
5. You can remove the program binaries and object files from the source code directory by typing `make clean'. To also remove the files that `configure' created (so you can compile the package for a different kind of computer), type `make distclean'. There is also a `make maintainer-clean' target, but that is intended mainly for the package's developers. If you use it, you may have to get all sorts of other programs in order to regenerate files that came with the distribution.
Synthesizable VHDL Model Library
We have implemented parameterizeable VHDL models and Testbenches.
You type in the portwidth and receive the synthesizeable VHDL description
(and the accordingly testbench and a trace filewww.ewalkins.com
